Radzhab Bisultanov
d59cf7cd55
Очередная попытка реализовать чтение IMU как в рабочей прошивке оказалась провальной. Поэтому было принято решение перенести проект на C++ и писать его подобно рабочей прошивке. Реализован драйвер для I2C. Добавлены файлы интерфейса IMU и конкретного ICM20948.
346 lines
14 KiB
C
346 lines
14 KiB
C
/**
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******************************************************************************
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* @file system_stm32g4xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32g4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the HSI (16 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | HSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 16000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 16000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* PLL_M | 1
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*-----------------------------------------------------------------------------
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* PLL_N | 16
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*-----------------------------------------------------------------------------
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* PLL_P | 7
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*-----------------------------------------------------------------------------
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* PLL_Q | 2
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*-----------------------------------------------------------------------------
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* PLL_R | 2
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*-----------------------------------------------------------------------------
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* Require 48MHz for RNG | Disabled
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32g4xx_system
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* @{
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*/
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/** @addtogroup STM32G4xx_System_Private_Includes
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* @{
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*/
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#include "stm32g4xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/* Note: Following vector table addresses must be defined in line with linker
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configuration. */
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/*!< Uncomment the following line if you need to relocate the vector table
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anywhere in Flash or Sram, else the vector table is kept at the automatic
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remap of boot address selected */
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/* #define USER_VECT_TAB_ADDRESS */
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#if defined(USER_VECT_TAB_ADDRESS)
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/*!< Uncomment the following line if you need to relocate your vector Table
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in Sram else user remap will be done in Flash. */
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/* #define VECT_TAB_SRAM */
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#if defined(VECT_TAB_SRAM)
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#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#else
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#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#endif /* VECT_TAB_SRAM */
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#if !defined(VECT_TAB_OFFSET)
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
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This value must be a multiple of 0x200. */
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#endif /* VECT_TAB_OFFSET */
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#endif /* USER_VECT_TAB_ADDRESS */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = HSI_VALUE;
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32G4xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
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* 24 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp, pllvco, pllr, pllsource, pllm;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x04: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
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if (pllsource == 0x02UL) /* HSI used as PLL clock source */
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{
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pllvco = (HSI_VALUE / pllm);
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}
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else /* HSE used as PLL clock source */
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{
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pllvco = (HSE_VALUE / pllm);
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
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SystemCoreClock = pllvco/pllr;
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break;
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default:
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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void SystemClock_Config() // STM32G431CBT6
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{
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// 1. Включить тактирование для интерфейса управления питанием (PWR)
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// Это действие необходимо совершать одним из первых.
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RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
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// 2. Установить задержку Flash ПЕРЕД любым увеличением частоты.
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// При переключении на PLL 170 МГц и Vcore Range 1 требуется 4 цикла ожидания.
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// Безопаснее установить это значение заранее, пока система работает на низкой частоте HSI.
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_ACR_LATENCY_4WS);
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// 3. Включить prefetch buffer, instruction cache и data cache для максимальной производительности.
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FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN;
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// 4. Включить и дождаться готовности HSI (16 МГц).
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// Это важно, даже если он уже включен по умолчанию, для явного контроля.
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RCC->CR |= RCC_CR_HSION;
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while(!(RCC->CR & RCC_CR_HSIRDY));
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// 5. Настроить масштабирование напряжения на Range 1 (High-performance).
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// Это необходимо для работы на высоких частотах.
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// ВАЖНО: Делать это ДО включения PLL и переключения на него.
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MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_CR1_VOS_0);
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// Ожидаем готовности регулятора напряжения (ухода флага VOSF).
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while ((PWR->SR2 & PWR_SR2_VOSF) != 0);
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// 6. Включить режим Range 1 Boost для частот > 150 МГц.
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// Согласно документации (Reference Manual), это нужно делать, когда система
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// тактируется от HSI/HSE, ДО включения PLL.
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PWR->CR5 |= PWR_CR5_R1MODE;
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// 7. Убедиться, что PLL выключен, перед его настройкой.
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RCC->CR &= ~RCC_CR_PLLON;
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while(RCC->CR & RCC_CR_PLLRDY);
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// 8. Настроить PLL для получения 170 МГц от HSI.
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// SYSCLK = (HSI / M) * N / R = (16МГц / 4) * 85 / 2 = 170 МГц
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// VCO = (HSI / M) * N = 4МГц * 85 = 340 МГц (в допустимом диапазоне 64..344 МГц)
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RCC->PLLCFGR = (RCC_PLLCFGR_PLLSRC_HSI | // Источник: HSI (16 МГц)
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(3 << RCC_PLLCFGR_PLLM_Pos) | // Предделитель M = 4 (записывается 3)
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(85 << RCC_PLLCFGR_PLLN_Pos) | // Множитель N = 85
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RCC_PLLCFGR_PLLREN); // Включить главный выход PLL 'R'
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// PLLR divider = 2 (по умолчанию, запись 0)
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// 9. Включить PLL и дождаться его готовности.
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RCC->CR |= RCC_CR_PLLON;
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while(!(RCC->CR & RCC_CR_PLLRDY));
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// 10. Переключить системные часы (SYSCLK) на PLL.
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_CFGR_SW_PLL);
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// Ожидаем подтверждения, что система действительно переключилась на PLL.
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while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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// 11. Обновить глобальную переменную с частотой ядра.
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// Это необходимо для корректной работы функций HAL/CMSIS (например, для настройки SysTick).
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SystemCoreClock = 170000000UL;
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}
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