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last_rab_alpha+hysteresis

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Co-authored-by: Copilot <copilot@github.com>
This commit is contained in:
vadyschka01
2026-05-08 15:21:04 +03:00
parent ef940ed92e
commit c4de796f82
20 changed files with 412 additions and 385 deletions
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.vscode/iar-vsc.json
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@@ -11,5 +11,8 @@
},
"workspace": {
"path": "${workspaceFolder}\\fft_az.eww"
},
"workbench": {
"path": "C:\\iar\\ewarm-9.70.1"
}
}
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Debug/.ninja_log
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@@ -1,75 +1,71 @@
# ninja log v6
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@@ -1,6 +1,6 @@
###############################################################################
#
# IAR ELF Linker V9.70.1.475/W64 for ARM 07/May/2026 18:06:49
# IAR ELF Linker V9.70.1.475/W64 for ARM 08/May/2026 15:10:39
# Copyright 2007-2025 IAR Systems AB.
#
# Output file =
@@ -79,7 +79,7 @@ No sections matched the following patterns:
.intvec ro code 0x800'0000 4 0x1d8 startup_stm32g431xx.o [1]
- 0x800'01d8 0x1d8
"P1": 0x1'fbd8
"P1": 0x1'fc24
.rodata const 0x800'01d8 4 0x8000 arm_common_tables.o [3]
.rodata const 0x800'81d8 4 0x4000 arm_common_tables.o [3]
.rodata const 0x800'c1d8 4 0x4000 arm_common_tables.o [3]
@@ -101,68 +101,49 @@ No sections matched the following patterns:
.rodata const 0x801'd634 4 0x400 arm_common_tables.o [3]
.rodata const 0x801'da34 4 0x380 arm_common_tables.o [3]
.rodata const 0x801'ddb4 4 0x370 arm_common_tables.o [3]
.text ro code 0x801'e124 4 0x298 imu.o [1]
.text ro code 0x801'e3bc 4 0x284 dsp_manager.o [1]
.text ro code 0x801'e640 4 0x1bc arm_rfft_fast_init_f32.o [3]
.text ro code 0x801'e7fc 4 0x90 arm_cos_f32.o [3]
.text ro code 0x801'e88c 4 0x10e arm_mult_f32.o [3]
.text ro code 0x801'e99c 4 0x182 arm_rfft_fast_f32.o [3]
.text ro code 0x801'eb20 4 0x154 arm_cmplx_mag_f32.o [3]
.text ro code 0x801'ec74 4 0x8c arm_sin_f32.o [3]
.text ro code 0x801'ed00 4 0x98 arm_cfft_init_f32.o [3]
.text ro code 0x801'ed98 4 0x214 main.o [1]
.text ro code 0x801'efac 4 0xc8 motors.o [1]
.text ro code 0x801'f074 4 0x9c system_stm32g4xx.o [1]
.rodata const 0x801'f110 4 0x200 arm_common_tables.o [3]
.rodata const 0x801'f310 4 0x200 arm_common_tables.o [3]
.rodata const 0x801'f510 4 0x1a0 arm_common_tables.o [3]
.rodata const 0x801'f6b0 4 0x100 arm_common_tables.o [3]
.rodata const 0x801'f7b0 4 0x100 arm_common_tables.o [3]
.rodata const 0x801'f8b0 4 0x80 arm_common_tables.o [3]
.rodata const 0x801'f930 4 0x80 arm_common_tables.o [3]
.rodata const 0x801'f9b0 4 0x70 arm_common_tables.o [3]
.rodata const 0x801'fa20 4 0x60 arm_common_tables.o [3]
.text ro code 0x801'fa80 2 0x38 zero_init3.o [5]
.rodata const 0x801'fab8 4 0x28 arm_common_tables.o [3]
.text ro code 0x801'fae0 4 0x28 data_init.o [5]
.text ro code 0x801'fb08 4 0x22 fpinit_M.o [4]
.text ro code 0x801'fb2c 4 0x22 cmain.o [5]
.text ro code 0x801'fb4e 2 0x4 low_level_init.o [2]
.text ro code 0x801'fb52 2 0x4 exit.o [2]
.text ro code 0x801'fb58 4 0x4 cexit.o [5]
.text ro code 0x801'fb5c 4 0xa cexit_2.o [5]
.text ro code 0x801'fb68 4 0x14 exit.o [6]
.iar.init_table const 0x801'fb7c 4 0x24 - Linker created -
.text ro code 0x801'fba0 4 0x1e cstartup_M.o [5]
.rodata const 0x801'fbc0 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fbd0 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fbe0 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fbf0 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc00 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc10 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc20 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc30 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc40 4 0x10 arm_const_structs.o [3]
.text ro code 0x801'fc50 4 0x10 startup_stm32g431xx.o [1]
.text ro code 0x801'fc60 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc64 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc68 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc6c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc70 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc74 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc78 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc7c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc80 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc84 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc88 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc8c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc90 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc94 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc98 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fc9c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fca0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fca4 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fca8 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'e124 4 0x2b4 dsp_manager.o [1]
.text ro code 0x801'e3d8 4 0x1bc arm_rfft_fast_init_f32.o [3]
.text ro code 0x801'e594 4 0x90 arm_cos_f32.o [3]
.text ro code 0x801'e624 4 0x10e arm_mult_f32.o [3]
.text ro code 0x801'e734 4 0x182 arm_rfft_fast_f32.o [3]
.text ro code 0x801'e8b8 4 0x154 arm_cmplx_mag_f32.o [3]
.text ro code 0x801'ea0c 4 0x2b4 imu.o [1]
.text ro code 0x801'ecc0 4 0x8c arm_sin_f32.o [3]
.text ro code 0x801'ed4c 4 0x98 arm_cfft_init_f32.o [3]
.text ro code 0x801'ede4 4 0x214 main.o [1]
.text ro code 0x801'eff8 4 0xc8 motors.o [1]
.text ro code 0x801'f0c0 4 0x9c system_stm32g4xx.o [1]
.rodata const 0x801'f15c 4 0x200 arm_common_tables.o [3]
.rodata const 0x801'f35c 4 0x200 arm_common_tables.o [3]
.rodata const 0x801'f55c 4 0x1a0 arm_common_tables.o [3]
.rodata const 0x801'f6fc 4 0x100 arm_common_tables.o [3]
.rodata const 0x801'f7fc 4 0x100 arm_common_tables.o [3]
.rodata const 0x801'f8fc 4 0x80 arm_common_tables.o [3]
.rodata const 0x801'f97c 4 0x80 arm_common_tables.o [3]
.rodata const 0x801'f9fc 4 0x70 arm_common_tables.o [3]
.rodata const 0x801'fa6c 4 0x60 arm_common_tables.o [3]
.text ro code 0x801'facc 2 0x38 zero_init3.o [5]
.rodata const 0x801'fb04 4 0x28 arm_common_tables.o [3]
.text ro code 0x801'fb2c 4 0x28 data_init.o [5]
.text ro code 0x801'fb54 4 0x22 fpinit_M.o [4]
.text ro code 0x801'fb78 4 0x22 cmain.o [5]
.text ro code 0x801'fb9a 2 0x4 low_level_init.o [2]
.text ro code 0x801'fb9e 2 0x4 exit.o [2]
.text ro code 0x801'fba4 4 0x4 cexit.o [5]
.text ro code 0x801'fba8 4 0xa cexit_2.o [5]
.text ro code 0x801'fbb4 4 0x14 exit.o [6]
.iar.init_table const 0x801'fbc8 4 0x24 - Linker created -
.text ro code 0x801'fbec 4 0x1e cstartup_M.o [5]
.rodata const 0x801'fc0c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc1c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc2c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc3c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc4c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc5c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc6c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc7c 4 0x10 arm_const_structs.o [3]
.rodata const 0x801'fc8c 4 0x10 arm_const_structs.o [3]
.text ro code 0x801'fc9c 4 0x10 startup_stm32g431xx.o [1]
.text ro code 0x801'fcac 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fcb0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fcb4 2 0x4 startup_stm32g431xx.o [1]
@@ -222,10 +203,29 @@ No sections matched the following patterns:
.text ro code 0x801'fd8c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fd90 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fd94 2 0x4 startup_stm32g431xx.o [1]
.rodata const 0x801'fd98 0x0 zero_init3.o [5]
.rodata const 0x801'fd98 0x0 copy_init3.o [5]
Initializer bytes const 0x801'fd98 4 0x18 <for P3 s0>
- 0x801'fdb0 0x1'fbd8
.text ro code 0x801'fd98 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fd9c 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fda0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fda4 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fda8 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdac 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdb0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdb4 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdb8 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdbc 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdc0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdc4 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdc8 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdcc 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdd0 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdd4 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fdd8 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fddc 2 0x4 startup_stm32g431xx.o [1]
.text ro code 0x801'fde0 2 0x4 startup_stm32g431xx.o [1]
.rodata const 0x801'fde4 0x0 zero_init3.o [5]
.rodata const 0x801'fde4 0x0 copy_init3.o [5]
Initializer bytes const 0x801'fde4 4 0x18 <for P3 s0>
- 0x801'fdfc 0x1'fc24
"P3", part 1 of 3: 0x18
P3 s0 0x2000'0000 0x18 <Init block>
@@ -249,7 +249,7 @@ Unused ranges:
From To Size
---- -- ----
0x801'fdb0 0x801'ffff 0x250
0x801'fdfc 0x801'ffff 0x204
0x2000'1cac 0x2000'1caf 0x4
0x2000'24b0 0x2000'3fff 0x1b50
0x2000'4000 0x2000'57ff 0x1800
@@ -267,7 +267,7 @@ Zero (__iar_zero_init3)
Copy (__iar_copy_init3)
1 source range, total size 0x18:
0x801'fd98 0x18
0x801'fde4 0x18
1 destination range, total size 0x18:
0x2000'0000 0x18
@@ -284,14 +284,14 @@ command line/config:
Total:
C:\Users\vadychka\Documents\GitHub\leybl\fft\Debug\Obj: [1]
dsp_manager.o 644 7'220
imu.o 664 96
dsp_manager.o 692 7'220
imu.o 692 96
main.o 532 20 20
motors.o 200
startup_stm32g431xx.o 800
system_stm32g4xx.o 156 4 4
---------------------------------------------------
Total: 2'996 24 7'340
Total: 3'072 24 7'340
dl7M_tln.a: [2]
exit.o 4
@@ -339,7 +339,7 @@ shb_l.a: [6]
Gaps 10 4
Linker created 36 2'048
-------------------------------------------------------
Grand Total: 8'452 122'028 9'388
Grand Total: 8'528 122'028 9'388
*******************************************************************************
@@ -348,204 +348,204 @@ shb_l.a: [6]
Entry Address Size Type Object
----- ------- ---- ---- ------
.iar.init_table$$Base 0x801'fb7c -- Gb - Linker created -
.iar.init_table$$Limit 0x801'fba0 -- Gb - Linker created -
?main 0x801'fb2d Code Gb cmain.o [5]
ADC1_2_IRQHandler 0x801'fcc9 Code Wk startup_stm32g431xx.o [1]
AHBPrescTable 0x801'f100 0x10 Data Gb system_stm32g4xx.o [1]
BusFault_Handler 0x801'fc6d Code Wk startup_stm32g431xx.o [1]
COMP1_2_3_IRQHandler 0x801'fd65 Code Wk startup_stm32g431xx.o [1]
COMP4_IRQHandler 0x801'fd69 Code Wk startup_stm32g431xx.o [1]
CORDIC_IRQHandler 0x801'fd91 Code Wk startup_stm32g431xx.o [1]
CRS_IRQHandler 0x801'fd6d Code Wk startup_stm32g431xx.o [1]
.iar.init_table$$Base 0x801'fbc8 -- Gb - Linker created -
.iar.init_table$$Limit 0x801'fbec -- Gb - Linker created -
?main 0x801'fb79 Code Gb cmain.o [5]
ADC1_2_IRQHandler 0x801'fd15 Code Wk startup_stm32g431xx.o [1]
AHBPrescTable 0x801'f14c 0x10 Data Gb system_stm32g4xx.o [1]
BusFault_Handler 0x801'fcb9 Code Wk startup_stm32g431xx.o [1]
COMP1_2_3_IRQHandler 0x801'fdb1 Code Wk startup_stm32g431xx.o [1]
COMP4_IRQHandler 0x801'fdb5 Code Wk startup_stm32g431xx.o [1]
CORDIC_IRQHandler 0x801'fddd Code Wk startup_stm32g431xx.o [1]
CRS_IRQHandler 0x801'fdb9 Code Wk startup_stm32g431xx.o [1]
CSTACK$$Base 0x2000'1cb0 -- Gb - Linker created -
CSTACK$$Limit 0x2000'24b0 -- Gb - Linker created -
DMA1_Channel1_IRQHandler
0x801'fcb1 Code Wk startup_stm32g431xx.o [1]
0x801'fcfd Code Wk startup_stm32g431xx.o [1]
DMA1_Channel2_IRQHandler
0x801'fcb5 Code Wk startup_stm32g431xx.o [1]
0x801'fd01 Code Wk startup_stm32g431xx.o [1]
DMA1_Channel3_IRQHandler
0x801'fcb9 Code Wk startup_stm32g431xx.o [1]
0x801'fd05 Code Wk startup_stm32g431xx.o [1]
DMA1_Channel4_IRQHandler
0x801'fcbd Code Wk startup_stm32g431xx.o [1]
0x801'fd09 Code Wk startup_stm32g431xx.o [1]
DMA1_Channel5_IRQHandler
0x801'fcc1 Code Wk startup_stm32g431xx.o [1]
0x801'fd0d Code Wk startup_stm32g431xx.o [1]
DMA1_Channel6_IRQHandler
0x801'fcc5 Code Wk startup_stm32g431xx.o [1]
0x801'fd11 Code Wk startup_stm32g431xx.o [1]
DMA2_Channel1_IRQHandler
0x801'fd4d Code Wk startup_stm32g431xx.o [1]
0x801'fd99 Code Wk startup_stm32g431xx.o [1]
DMA2_Channel2_IRQHandler
0x801'fd51 Code Wk startup_stm32g431xx.o [1]
0x801'fd9d Code Wk startup_stm32g431xx.o [1]
DMA2_Channel3_IRQHandler
0x801'fd55 Code Wk startup_stm32g431xx.o [1]
0x801'fda1 Code Wk startup_stm32g431xx.o [1]
DMA2_Channel4_IRQHandler
0x801'fd59 Code Wk startup_stm32g431xx.o [1]
0x801'fda5 Code Wk startup_stm32g431xx.o [1]
DMA2_Channel5_IRQHandler
0x801'fd5d Code Wk startup_stm32g431xx.o [1]
0x801'fda9 Code Wk startup_stm32g431xx.o [1]
DMA2_Channel6_IRQHandler
0x801'fd8d Code Wk startup_stm32g431xx.o [1]
DMAMUX_OVR_IRQHandler 0x801'fd89 Code Wk startup_stm32g431xx.o [1]
DSP_AddSample 0x801'e40d 0x2c Code Gb dsp_manager.o [1]
DSP_Init 0x801'e3bd 0x50 Code Gb dsp_manager.o [1]
DSP_Process 0x801'e439 0x1d2 Code Gb dsp_manager.o [1]
DebugMon_Handler 0x801'fc79 Code Wk startup_stm32g431xx.o [1]
EXTI0_IRQHandler 0x801'fc9d Code Wk startup_stm32g431xx.o [1]
EXTI15_10_IRQHandler 0x801'fd21 Code Wk startup_stm32g431xx.o [1]
EXTI1_IRQHandler 0x801'fca1 Code Wk startup_stm32g431xx.o [1]
EXTI2_IRQHandler 0x801'fca5 Code Wk startup_stm32g431xx.o [1]
EXTI3_IRQHandler 0x801'fca9 Code Wk startup_stm32g431xx.o [1]
EXTI4_IRQHandler 0x801'fcad Code Wk startup_stm32g431xx.o [1]
EXTI9_5_IRQHandler 0x801'fcdd Code Wk startup_stm32g431xx.o [1]
FDCAN1_IT0_IRQHandler 0x801'fcd5 Code Wk startup_stm32g431xx.o [1]
FDCAN1_IT1_IRQHandler 0x801'fcd9 Code Wk startup_stm32g431xx.o [1]
FLASH_IRQHandler 0x801'fc95 Code Wk startup_stm32g431xx.o [1]
FMAC_IRQHandler 0x801'fd95 Code Wk startup_stm32g431xx.o [1]
FMAC_Init 0x801'e125 0x4a Code Gb imu.o [1]
FPU_IRQHandler 0x801'fd75 Code Wk startup_stm32g431xx.o [1]
HardFault_Handler 0x801'fc65 Code Wk startup_stm32g431xx.o [1]
I2C1_ER_IRQHandler 0x801'fd01 Code Wk startup_stm32g431xx.o [1]
I2C1_EV_IRQHandler 0x801'fcfd Code Wk startup_stm32g431xx.o [1]
I2C1_Init 0x801'e16f 0x4c Code Gb imu.o [1]
I2C2_ER_IRQHandler 0x801'fd09 Code Wk startup_stm32g431xx.o [1]
I2C2_EV_IRQHandler 0x801'fd05 Code Wk startup_stm32g431xx.o [1]
I2C3_ER_IRQHandler 0x801'fd85 Code Wk startup_stm32g431xx.o [1]
I2C3_EV_IRQHandler 0x801'fd81 Code Wk startup_stm32g431xx.o [1]
I2C_ReadMulti 0x801'e1bb 0x40 Code Gb imu.o [1]
IMU_Calibrate 0x801'e2d1 0x4c Code Gb imu.o [1]
IMU_Init 0x801'e26b 0x66 Code Gb imu.o [1]
IMU_ReadRawData 0x801'e31d 0x54 Code Gb imu.o [1]
IMU_SetBank 0x801'e223 0xa Code Gb imu.o [1]
IMU_WriteReg 0x801'e1fb 0x28 Code Lc imu.o [1]
LPTIM1_IRQHandler 0x801'fd3d Code Wk startup_stm32g431xx.o [1]
LPUART1_IRQHandler 0x801'fd7d Code Wk startup_stm32g431xx.o [1]
MemManage_Handler 0x801'fc69 Code Wk startup_stm32g431xx.o [1]
Motors_Init 0x801'efad 0x9a Code Gb motors.o [1]
NMI_Handler 0x801'fc61 Code Wk startup_stm32g431xx.o [1]
PVD_PVM_IRQHandler 0x801'fc89 Code Wk startup_stm32g431xx.o [1]
PendSV_Handler 0x801'fc7d Code Wk startup_stm32g431xx.o [1]
RCC_IRQHandler 0x801'fc99 Code Wk startup_stm32g431xx.o [1]
RNG_IRQHandler 0x801'fd79 Code Wk startup_stm32g431xx.o [1]
RTC_Alarm_IRQHandler 0x801'fd25 Code Wk startup_stm32g431xx.o [1]
0x801'fdd9 Code Wk startup_stm32g431xx.o [1]
DMAMUX_OVR_IRQHandler 0x801'fdd5 Code Wk startup_stm32g431xx.o [1]
DSP_AddSample 0x801'e175 0x2c Code Gb dsp_manager.o [1]
DSP_Init 0x801'e125 0x50 Code Gb dsp_manager.o [1]
DSP_Process 0x801'e1a1 0x1fc Code Gb dsp_manager.o [1]
DebugMon_Handler 0x801'fcc5 Code Wk startup_stm32g431xx.o [1]
EXTI0_IRQHandler 0x801'fce9 Code Wk startup_stm32g431xx.o [1]
EXTI15_10_IRQHandler 0x801'fd6d Code Wk startup_stm32g431xx.o [1]
EXTI1_IRQHandler 0x801'fced Code Wk startup_stm32g431xx.o [1]
EXTI2_IRQHandler 0x801'fcf1 Code Wk startup_stm32g431xx.o [1]
EXTI3_IRQHandler 0x801'fcf5 Code Wk startup_stm32g431xx.o [1]
EXTI4_IRQHandler 0x801'fcf9 Code Wk startup_stm32g431xx.o [1]
EXTI9_5_IRQHandler 0x801'fd29 Code Wk startup_stm32g431xx.o [1]
FDCAN1_IT0_IRQHandler 0x801'fd21 Code Wk startup_stm32g431xx.o [1]
FDCAN1_IT1_IRQHandler 0x801'fd25 Code Wk startup_stm32g431xx.o [1]
FLASH_IRQHandler 0x801'fce1 Code Wk startup_stm32g431xx.o [1]
FMAC_IRQHandler 0x801'fde1 Code Wk startup_stm32g431xx.o [1]
FMAC_Init 0x801'ea0d 0x4a Code Gb imu.o [1]
FPU_IRQHandler 0x801'fdc1 Code Wk startup_stm32g431xx.o [1]
HardFault_Handler 0x801'fcb1 Code Wk startup_stm32g431xx.o [1]
I2C1_ER_IRQHandler 0x801'fd4d Code Wk startup_stm32g431xx.o [1]
I2C1_EV_IRQHandler 0x801'fd49 Code Wk startup_stm32g431xx.o [1]
I2C1_Init 0x801'ea57 0x4c Code Gb imu.o [1]
I2C2_ER_IRQHandler 0x801'fd55 Code Wk startup_stm32g431xx.o [1]
I2C2_EV_IRQHandler 0x801'fd51 Code Wk startup_stm32g431xx.o [1]
I2C3_ER_IRQHandler 0x801'fdd1 Code Wk startup_stm32g431xx.o [1]
I2C3_EV_IRQHandler 0x801'fdcd Code Wk startup_stm32g431xx.o [1]
I2C_ReadMulti 0x801'eaa3 0x40 Code Gb imu.o [1]
IMU_Calibrate 0x801'ebb9 0x4c Code Gb imu.o [1]
IMU_Init 0x801'eb53 0x66 Code Gb imu.o [1]
IMU_ReadRawData 0x801'ec05 0x54 Code Gb imu.o [1]
IMU_SetBank 0x801'eb0b 0xa Code Gb imu.o [1]
IMU_WriteReg 0x801'eae3 0x28 Code Lc imu.o [1]
LPTIM1_IRQHandler 0x801'fd89 Code Wk startup_stm32g431xx.o [1]
LPUART1_IRQHandler 0x801'fdc9 Code Wk startup_stm32g431xx.o [1]
MemManage_Handler 0x801'fcb5 Code Wk startup_stm32g431xx.o [1]
Motors_Init 0x801'eff9 0x9a Code Gb motors.o [1]
NMI_Handler 0x801'fcad Code Wk startup_stm32g431xx.o [1]
PVD_PVM_IRQHandler 0x801'fcd5 Code Wk startup_stm32g431xx.o [1]
PendSV_Handler 0x801'fcc9 Code Wk startup_stm32g431xx.o [1]
RCC_IRQHandler 0x801'fce5 Code Wk startup_stm32g431xx.o [1]
RNG_IRQHandler 0x801'fdc5 Code Wk startup_stm32g431xx.o [1]
RTC_Alarm_IRQHandler 0x801'fd71 Code Wk startup_stm32g431xx.o [1]
RTC_TAMP_LSECSS_IRQHandler
0x801'fc8d Code Wk startup_stm32g431xx.o [1]
RTC_WKUP_IRQHandler 0x801'fc91 Code Wk startup_stm32g431xx.o [1]
Region$$Table$$Base 0x801'fb7c -- Gb - Linker created -
Region$$Table$$Limit 0x801'fba0 -- Gb - Linker created -
Reset_Handler 0x801'fc51 Code Wk startup_stm32g431xx.o [1]
SAI1_IRQHandler 0x801'fd71 Code Wk startup_stm32g431xx.o [1]
SPI1_IRQHandler 0x801'fd0d Code Wk startup_stm32g431xx.o [1]
SPI2_IRQHandler 0x801'fd11 Code Wk startup_stm32g431xx.o [1]
SPI3_IRQHandler 0x801'fd41 Code Wk startup_stm32g431xx.o [1]
SVC_Handler 0x801'fc75 Code Wk startup_stm32g431xx.o [1]
Set_Motor_Individual 0x801'f055 0x10 Code Gb motors.o [1]
Set_Motors 0x801'f047 0xe Code Gb motors.o [1]
SysTick_Handler 0x801'fc81 Code Wk startup_stm32g431xx.o [1]
0x801'fcd9 Code Wk startup_stm32g431xx.o [1]
RTC_WKUP_IRQHandler 0x801'fcdd Code Wk startup_stm32g431xx.o [1]
Region$$Table$$Base 0x801'fbc8 -- Gb - Linker created -
Region$$Table$$Limit 0x801'fbec -- Gb - Linker created -
Reset_Handler 0x801'fc9d Code Wk startup_stm32g431xx.o [1]
SAI1_IRQHandler 0x801'fdbd Code Wk startup_stm32g431xx.o [1]
SPI1_IRQHandler 0x801'fd59 Code Wk startup_stm32g431xx.o [1]
SPI2_IRQHandler 0x801'fd5d Code Wk startup_stm32g431xx.o [1]
SPI3_IRQHandler 0x801'fd8d Code Wk startup_stm32g431xx.o [1]
SVC_Handler 0x801'fcc1 Code Wk startup_stm32g431xx.o [1]
Set_Motor_Individual 0x801'f0a1 0x10 Code Gb motors.o [1]
Set_Motors 0x801'f093 0xe Code Gb motors.o [1]
SysTick_Handler 0x801'fccd Code Wk startup_stm32g431xx.o [1]
SystemClock_Config_160MHz
0x801'ee79 0x4c Code Gb main.o [1]
0x801'eec5 0x4c Code Gb main.o [1]
SystemCoreClock 0x2000'0014 0x4 Data Gb system_stm32g4xx.o [1]
SystemCoreClockUpdate 0x801'f081 0x6c Code Gb system_stm32g4xx.o [1]
SystemInit 0x801'f075 0xc Code Gb system_stm32g4xx.o [1]
SystemCoreClockUpdate 0x801'f0cd 0x6c Code Gb system_stm32g4xx.o [1]
SystemInit 0x801'f0c1 0xc Code Gb system_stm32g4xx.o [1]
TIM1_BRK_TIM15_IRQHandler
0x801'fce1 Code Wk startup_stm32g431xx.o [1]
TIM1_CC_IRQHandler 0x801'fced Code Wk startup_stm32g431xx.o [1]
0x801'fd2d Code Wk startup_stm32g431xx.o [1]
TIM1_CC_IRQHandler 0x801'fd39 Code Wk startup_stm32g431xx.o [1]
TIM1_TRG_COM_TIM17_IRQHandler
0x801'fce9 Code Wk startup_stm32g431xx.o [1]
TIM1_UP_TIM16_IRQHandler
0x801'fce5 Code Wk startup_stm32g431xx.o [1]
TIM2_IRQHandler 0x801'fcf1 Code Wk startup_stm32g431xx.o [1]
TIM3_IRQHandler 0x801'fcf5 Code Wk startup_stm32g431xx.o [1]
TIM4_IRQHandler 0x801'fcf9 Code Wk startup_stm32g431xx.o [1]
TIM6_DAC_IRQHandler 0x801'ef59 0x14 Code Gb main.o [1]
TIM6_Init_1000Hz 0x801'ef29 0x30 Code Gb main.o [1]
TIM7_IRQHandler 0x801'fd49 Code Wk startup_stm32g431xx.o [1]
TIM8_BRK_IRQHandler 0x801'fd2d Code Wk startup_stm32g431xx.o [1]
TIM8_CC_IRQHandler 0x801'fd39 Code Wk startup_stm32g431xx.o [1]
TIM8_TRG_COM_IRQHandler
0x801'fd35 Code Wk startup_stm32g431xx.o [1]
TIM8_UP_IRQHandler 0x801'fd31 Code Wk startup_stm32g431xx.o [1]
UART2_Init_921600 0x801'eec5 0x48 Code Gb main.o [1]
UART4_IRQHandler 0x801'fd45 Code Wk startup_stm32g431xx.o [1]
UART_SendPacket 0x801'ef0d 0x1c Code Gb main.o [1]
UCPD1_IRQHandler 0x801'fd61 Code Wk startup_stm32g431xx.o [1]
USART1_IRQHandler 0x801'fd15 Code Wk startup_stm32g431xx.o [1]
USART2_IRQHandler 0x801'fd19 Code Wk startup_stm32g431xx.o [1]
USART3_IRQHandler 0x801'fd1d Code Wk startup_stm32g431xx.o [1]
USBWakeUp_IRQHandler 0x801'fd29 Code Wk startup_stm32g431xx.o [1]
USB_HP_IRQHandler 0x801'fccd Code Wk startup_stm32g431xx.o [1]
USB_LP_IRQHandler 0x801'fcd1 Code Wk startup_stm32g431xx.o [1]
Update_FMAC_Coeffs 0x801'e371 0x22 Code Gb imu.o [1]
UsageFault_Handler 0x801'fc71 Code Wk startup_stm32g431xx.o [1]
WWDG_IRQHandler 0x801'fc85 Code Wk startup_stm32g431xx.o [1]
__cmain 0x801'fb2d Code Gb cmain.o [5]
__exit 0x801'fb69 0x14 Code Gb exit.o [6]
TIM1_UP_TIM16_IRQHandler
0x801'fd31 Code Wk startup_stm32g431xx.o [1]
TIM2_IRQHandler 0x801'fd3d Code Wk startup_stm32g431xx.o [1]
TIM3_IRQHandler 0x801'fd41 Code Wk startup_stm32g431xx.o [1]
TIM4_IRQHandler 0x801'fd45 Code Wk startup_stm32g431xx.o [1]
TIM6_DAC_IRQHandler 0x801'efa5 0x14 Code Gb main.o [1]
TIM6_Init_1000Hz 0x801'ef75 0x30 Code Gb main.o [1]
TIM7_IRQHandler 0x801'fd95 Code Wk startup_stm32g431xx.o [1]
TIM8_BRK_IRQHandler 0x801'fd79 Code Wk startup_stm32g431xx.o [1]
TIM8_CC_IRQHandler 0x801'fd85 Code Wk startup_stm32g431xx.o [1]
TIM8_TRG_COM_IRQHandler
0x801'fd81 Code Wk startup_stm32g431xx.o [1]
TIM8_UP_IRQHandler 0x801'fd7d Code Wk startup_stm32g431xx.o [1]
UART2_Init_921600 0x801'ef11 0x48 Code Gb main.o [1]
UART4_IRQHandler 0x801'fd91 Code Wk startup_stm32g431xx.o [1]
UART_SendPacket 0x801'ef59 0x1c Code Gb main.o [1]
UCPD1_IRQHandler 0x801'fdad Code Wk startup_stm32g431xx.o [1]
USART1_IRQHandler 0x801'fd61 Code Wk startup_stm32g431xx.o [1]
USART2_IRQHandler 0x801'fd65 Code Wk startup_stm32g431xx.o [1]
USART3_IRQHandler 0x801'fd69 Code Wk startup_stm32g431xx.o [1]
USBWakeUp_IRQHandler 0x801'fd75 Code Wk startup_stm32g431xx.o [1]
USB_HP_IRQHandler 0x801'fd19 Code Wk startup_stm32g431xx.o [1]
USB_LP_IRQHandler 0x801'fd1d Code Wk startup_stm32g431xx.o [1]
Update_FMAC_Coeffs 0x801'ec5d 0x38 Code Gb imu.o [1]
UsageFault_Handler 0x801'fcbd Code Wk startup_stm32g431xx.o [1]
WWDG_IRQHandler 0x801'fcd1 Code Wk startup_stm32g431xx.o [1]
__cmain 0x801'fb79 Code Gb cmain.o [5]
__exit 0x801'fbb5 0x14 Code Gb exit.o [6]
__iar_copy_init3 0x801'd1c3 0x2a Code Gb copy_init3.o [5]
__iar_data_init3 0x801'fae1 0x28 Code Gb data_init.o [5]
__iar_init_vfp 0x801'fb09 Code Gb fpinit_M.o [4]
__iar_program_start 0x801'fba1 Code Gb cstartup_M.o [5]
__iar_zero_init3 0x801'fa81 0x38 Code Gb zero_init3.o [5]
__low_level_init 0x801'fb4f 0x4 Code Gb low_level_init.o [2]
__iar_data_init3 0x801'fb2d 0x28 Code Gb data_init.o [5]
__iar_init_vfp 0x801'fb55 Code Gb fpinit_M.o [4]
__iar_program_start 0x801'fbed Code Gb cstartup_M.o [5]
__iar_zero_init3 0x801'facd 0x38 Code Gb zero_init3.o [5]
__low_level_init 0x801'fb9b 0x4 Code Gb low_level_init.o [2]
__vector_table 0x800'0000 Data Gb startup_stm32g431xx.o [1]
_call_main 0x801'fb39 Code Gb cmain.o [5]
_exit 0x801'fb59 Code Gb cexit.o [5]
_exit_2 0x801'fb5d Code Gb cexit_2.o [5]
_call_main 0x801'fb85 Code Gb cmain.o [5]
_exit 0x801'fba5 Code Gb cexit.o [5]
_exit_2 0x801'fba9 Code Gb cexit_2.o [5]
active_notch_freqs 0x2000'0418 0xc Data Gb dsp_manager.o [1]
armBitRevIndexTable1024
0x801'9f18 0xe10 Data Gb arm_common_tables.o [3]
armBitRevIndexTable128 0x801'f510 0x1a0 Data Gb arm_common_tables.o [3]
armBitRevIndexTable16 0x801'fab8 0x28 Data Gb arm_common_tables.o [3]
armBitRevIndexTable128 0x801'f55c 0x1a0 Data Gb arm_common_tables.o [3]
armBitRevIndexTable16 0x801'fb04 0x28 Data Gb arm_common_tables.o [3]
armBitRevIndexTable2048
0x801'6158 0x1dc0 Data Gb arm_common_tables.o [3]
armBitRevIndexTable256 0x801'ddb4 0x370 Data Gb arm_common_tables.o [3]
armBitRevIndexTable32 0x801'fa20 0x60 Data Gb arm_common_tables.o [3]
armBitRevIndexTable32 0x801'fa6c 0x60 Data Gb arm_common_tables.o [3]
armBitRevIndexTable4096
0x801'41d8 0x1f80 Data Gb arm_common_tables.o [3]
armBitRevIndexTable512 0x801'da34 0x380 Data Gb arm_common_tables.o [3]
armBitRevIndexTable64 0x801'f9b0 0x70 Data Gb arm_common_tables.o [3]
armBitRevIndexTable64 0x801'f9fc 0x70 Data Gb arm_common_tables.o [3]
arm_bitreversal_32 0x801'd1ed 0x46 Code Gb arm_bitreversal2.o [3]
arm_cfft_f32 0x801'caad 0x184 Code Gb arm_cfft_f32.o [3]
arm_cfft_init_f32 0x801'ed01 0x98 Code Gb arm_cfft_init_f32.o [3]
arm_cfft_init_f32 0x801'ed4d 0x98 Code Gb arm_cfft_init_f32.o [3]
arm_cfft_radix8by2_f32 0x801'c52d 0x16a Code Gb arm_cfft_f32.o [3]
arm_cfft_radix8by4_f32 0x801'c699 0x412 Code Gb arm_cfft_f32.o [3]
arm_cfft_sR_f32_len1024
0x801'fc20 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len128 0x801'fbf0 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len16 0x801'fbc0 0x10 Data Gb arm_const_structs.o [3]
0x801'fc6c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len128 0x801'fc3c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len16 0x801'fc0c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len2048
0x801'fc30 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len256 0x801'fc00 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len32 0x801'fbd0 0x10 Data Gb arm_const_structs.o [3]
0x801'fc7c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len256 0x801'fc4c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len32 0x801'fc1c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len4096
0x801'fc40 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len512 0x801'fc10 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len64 0x801'fbe0 0x10 Data Gb arm_const_structs.o [3]
arm_cmplx_mag_f32 0x801'eb21 0x154 Code Gb arm_cmplx_mag_f32.o [3]
arm_cos_f32 0x801'e7fd 0x90 Code Gb arm_cos_f32.o [3]
arm_mult_f32 0x801'e88d 0x10e Code Gb arm_mult_f32.o [3]
0x801'fc8c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len512 0x801'fc5c 0x10 Data Gb arm_const_structs.o [3]
arm_cfft_sR_f32_len64 0x801'fc2c 0x10 Data Gb arm_const_structs.o [3]
arm_cmplx_mag_f32 0x801'e8b9 0x154 Code Gb arm_cmplx_mag_f32.o [3]
arm_cos_f32 0x801'e595 0x90 Code Gb arm_cos_f32.o [3]
arm_mult_f32 0x801'e625 0x10e Code Gb arm_mult_f32.o [3]
arm_radix8_butterfly_f32
0x801'cc31 0x592 Code Gb arm_cfft_radix8_f32.o [3]
arm_rfft_1024_fast_init_f32
0x801'e6f1 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e489 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_128_fast_init_f32
0x801'e685 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e41d 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_2048_fast_init_f32
0x801'e717 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e4af 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_256_fast_init_f32
0x801'e6a7 0x24 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e43f 0x24 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_32_fast_init_f32
0x801'e641 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e3d9 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_4096_fast_init_f32
0x801'e73d 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e4d5 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_512_fast_init_f32
0x801'e6cb 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
0x801'e463 0x26 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_64_fast_init_f32
0x801'e663 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_fast_f32 0x801'eae5 0x3a Code Gb arm_rfft_fast_f32.o [3]
arm_rfft_fast_init_f32 0x801'e763 0x5a Code Gb arm_rfft_fast_init_f32.o [3]
arm_sin_f32 0x801'ec75 0x8c Code Gb arm_sin_f32.o [3]
biquad_apply 0x801'e22d 0x3e Code Gb imu.o [1]
0x801'e3fb 0x22 Code Lc arm_rfft_fast_init_f32.o [3]
arm_rfft_fast_f32 0x801'e87d 0x3a Code Gb arm_rfft_fast_f32.o [3]
arm_rfft_fast_init_f32 0x801'e4fb 0x5a Code Gb arm_rfft_fast_init_f32.o [3]
arm_sin_f32 0x801'ecc1 0x8c Code Gb arm_sin_f32.o [3]
biquad_apply 0x801'eb15 0x3e Code Gb imu.o [1]
dsp_buffer_ready 0x2000'0c30 0x1 Data Gb dsp_manager.o [1]
dyn_notch_filters 0x2000'1c50 0x54 Data Gb imu.o [1]
exit 0x801'fb53 0x4 Code Gb exit.o [2]
exit 0x801'fb9f 0x4 Code Gb exit.o [2]
fft_handler 0x2000'1434 0x18 Data Lc dsp_manager.o [1]
fft_input 0x2000'144c 0x800 Data Lc dsp_manager.o [1]
fft_output 0x2000'0430 0x800 Data Lc dsp_manager.o [1]
@@ -558,30 +558,30 @@ m2_speed 0x2000'0008 0x4 Data Gb main.o [1]
m3_speed 0x2000'000c 0x4 Data Gb main.o [1]
m4_speed 0x2000'0010 0x4 Data Gb main.o [1]
magnitudes 0x2000'0018 0x400 Data Lc dsp_manager.o [1]
main 0x801'ed99 0xe0 Code Gb main.o [1]
merge_rfft_f32 0x801'ea45 0xa0 Code Gb arm_rfft_fast_f32.o [3]
main 0x801'ede5 0xe0 Code Gb main.o [1]
merge_rfft_f32 0x801'e7dd 0xa0 Code Gb arm_rfft_fast_f32.o [3]
raw_gx 0x2000'1c4c 0x2 Data Gb imu.o [1]
sample_count 0x2000'0c32 0x2 Data Lc dsp_manager.o [1]
sinTable_f32 0x801'ad28 0x804 Data Gb arm_common_tables.o [3]
smoothed_freqs 0x2000'0424 0xc Data Lc dsp_manager.o [1]
stage_rfft_f32 0x801'e99d 0xa8 Code Gb arm_rfft_fast_f32.o [3]
stage_rfft_f32 0x801'e735 0xa8 Code Gb arm_rfft_fast_f32.o [3]
twiddleCoef_1024 0x801'01d8 0x2000 Data Gb arm_common_tables.o [3]
twiddleCoef_128 0x801'd234 0x400 Data Gb arm_common_tables.o [3]
twiddleCoef_16 0x801'f8b0 0x80 Data Gb arm_common_tables.o [3]
twiddleCoef_16 0x801'f8fc 0x80 Data Gb arm_common_tables.o [3]
twiddleCoef_2048 0x800'81d8 0x4000 Data Gb arm_common_tables.o [3]
twiddleCoef_256 0x801'b52c 0x800 Data Gb arm_common_tables.o [3]
twiddleCoef_32 0x801'f6b0 0x100 Data Gb arm_common_tables.o [3]
twiddleCoef_32 0x801'f6fc 0x100 Data Gb arm_common_tables.o [3]
twiddleCoef_4096 0x800'01d8 0x8000 Data Gb arm_common_tables.o [3]
twiddleCoef_512 0x801'7f18 0x1000 Data Gb arm_common_tables.o [3]
twiddleCoef_64 0x801'f110 0x200 Data Gb arm_common_tables.o [3]
twiddleCoef_64 0x801'f15c 0x200 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_1024 0x801'8f18 0x1000 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_128 0x801'f310 0x200 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_128 0x801'f35c 0x200 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_2048 0x801'21d8 0x2000 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_256 0x801'd634 0x400 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_32 0x801'f930 0x80 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_32 0x801'f97c 0x80 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_4096 0x800'c1d8 0x4000 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_512 0x801'bd2c 0x800 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_64 0x801'f7b0 0x100 Data Gb arm_common_tables.o [3]
twiddleCoef_rfft_64 0x801'f7fc 0x100 Data Gb arm_common_tables.o [3]
[1] = C:\Users\vadychka\Documents\GitHub\leybl\fft\Debug\Obj
@@ -591,7 +591,7 @@ twiddleCoef_rfft_64 0x801'f7b0 0x100 Data Gb arm_common_tables.o [3]
[5] = rt7M_tl.a
[6] = shb_l.a
8'452 bytes of readonly code memory
8'528 bytes of readonly code memory
122'028 bytes of readonly data memory
9'388 bytes of readwrite data memory
Debug/Obj/dsp_manager.o
BIN
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Debug/Obj/imu.o
BIN
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Debug/Obj/main.o
BIN
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dsp_manager.c
+17 -10
View File
@@ -6,7 +6,7 @@ static float32_t fft_input[FFT_SIZE];
static float32_t fft_output[FFT_SIZE];
static float32_t magnitudes[FFT_SIZE / 2];
// Буфер для окна Ханна (чтобы убрать шумы по краям выборки)
// Буфер для окна Ханна (убрать шумы по краям выборки)
static float32_t hann_window[FFT_SIZE];
static uint16_t sample_count = 0;
@@ -20,7 +20,7 @@ float active_notch_freqs[3] = {0.0f, 0.0f, 0.0f};
//альфа
static float32_t smoothed_freqs[3] = {0.0f, 0.0f, 0.0f};
#define FREQ_ALPHA 0.05f // Чем МЕНЬШЕ значение, тем дольше фильтр "едет" к новой частоте
#define FREQ_ALPHA 0.05f // время зависания nocha на частотном пике
void DSP_Init(void) {
// Инициализируем структуру БПФ
@@ -33,13 +33,13 @@ void DSP_Init(void) {
}
void DSP_AddSample(float32_t sample) {
if (dsp_buffer_ready) return; // Ждем, пока обработают прошлую пачку
if (dsp_buffer_ready) return; // ожидание обработки прошлой пачки
fft_input[sample_count++] = sample;
if (sample_count >= FFT_SIZE) {
sample_count = 0;
dsp_buffer_ready = 1; // Сигнализируем в main
dsp_buffer_ready = 1; // Сигнал в main
}
}
@@ -57,10 +57,10 @@ void DSP_Process(void) {
float32_t top_freq_indices[3] = {0};
float32_t top_mags[3] = {0};
// Индексы для поиска от 50 Гц до 450 Гц
// Индексы для поиска примерно от 95 Гц до 480 Гц
// index = freq * FFT_SIZE / fs = freq * 512 / 1000
uint32_t start_idx = 25; // ~50 Гц (50 * 512 / 1000 = 25)
uint32_t end_idx = 230; // ~450 Гц (450 * 512 / 1000 = 230)
uint32_t start_idx = 48; // ~94 Гц (95 * 512 / 1000 = 48.6)
uint32_t end_idx = 245; // ~479 Гц (480 * 512 / 1000 = 245.8)
for (int k = 0; k < 3; k++) {
float32_t max_m = 0;
@@ -90,7 +90,7 @@ void DSP_Process(void) {
// --- 5. ПЕРЕНАСТРОЙКА ТРЕХ КАСКАДОВ FMAC ---
const float fs = 1000.0f; // Частота дискретизации
const float Q = 3.5f; // Добротность
const float Q = 2.5f; // Добротность (уменьшена для расширения ямы, чтобы соседние пики подавлялись)
const float bin_to_hz = fs / (float)FFT_SIZE;
for (int i = 0; i < 3; i++) {
@@ -101,7 +101,7 @@ void DSP_Process(void) {
// Если фильтр сейчас ВЫКЛЮЧЕН (active_notch_freqs == 0)
if (active_notch_freqs[i] == 0) {
if (mag > 4000.0f) {
// Включаем фильтр! Чтобы не полз с нуля, присваиваем частоту сразу:
// Включаем фильтр. Чтобы не полз с нуля, присваиваем частоту сразу:
smoothed_freqs[i] = new_freq;
active_notch_freqs[i] = new_freq;
}
@@ -113,7 +113,14 @@ void DSP_Process(void) {
active_notch_freqs[i] = 0;
} else {
// Продолжаем отслеживать с Альфой (EMA)
smoothed_freqs[i] = (smoothed_freqs[i] * (1.0f - FREQ_ALPHA)) + (new_freq * FREQ_ALPHA);
if (fabsf(new_freq - smoothed_freqs[i]) > 20.0f) {
// Большой прыжок частоты: сбрасываем память фильтра, чтобы не тянуть старый хвост
dyn_notch_filters[i].d1 = 0.0f;
dyn_notch_filters[i].d2 = 0.0f;
smoothed_freqs[i] = new_freq;
} else {
smoothed_freqs[i] = (smoothed_freqs[i] * (1.0f - FREQ_ALPHA)) + (new_freq * FREQ_ALPHA);
}
active_notch_freqs[i] = smoothed_freqs[i];
}
}
imu.c
+13 -7
View File
@@ -22,8 +22,7 @@
#define FMAC_MEM_SIZE 256
#define STAGE_SIZE 10 // Резервируем с запасом под каждый каскад
// raw_ax, raw_ay, raw_az удалены (не используются)
volatile int16_t raw_gx; // Нужен только для гироскопа X
volatile int16_t raw_gx; // только гироскопа X
float filt_gx;
float gyro_bias_x = 0;
@@ -127,7 +126,7 @@ void IMU_Init(void) {
// Значение GYRO_DLPFCFG = 7 для макс. ширины без полного байпаса: ~361.4 Hz LPF.
// (0 - это 196Hz, 1 - 151Hz, 2 - 119Hz, 3 - 51Hz, 7 - 361.4Hz)
// GYRO_FS_SEL = 3 (2000 dps)
// ВНИМАНИЕ: На ICM-20948 бит GYRO_FCHOICE (бит 0) включает LPF, если равен 1! (а 0 = Bypass)
// ВНИМАНИЕ: На ICM-20948 бит GYRO_FCHOICE (бит 0) включает LPF, если равен 1. (а 0 = Bypass)
IMU_WriteReg(0x01, (7 << 3) | (3 << 1) | 1);
IMU_SetBank(0);
@@ -164,16 +163,16 @@ void IMU_ReadRawData(void) {
// 2. Центрируем относительно нуля (убираем дрейф)
float x = (float)gyro_x_raw - gyro_bias_x;
// 3. СОХРАНЯЕМ это в raw_gx (это будет красная линия в Python)
// 3. Сохраняем это в raw_gx
raw_gx = (int16_t)x;
// 4. Прогоняем через 3 каскада программных фильтров (режекторные)
// 4. Прогоняем через 3 каскада программных фильтров (режектор)
float x_filtered = x;
x_filtered = biquad_apply(&dyn_notch_filters[0], x_filtered);
x_filtered = biquad_apply(&dyn_notch_filters[1], x_filtered);
x_filtered = biquad_apply(&dyn_notch_filters[2], x_filtered);
// 5. Сохраняем в filt_gx (это будет синяя линия)
// 5. Сохраняем в filt_gx
filt_gx = x_filtered;
}
@@ -186,6 +185,13 @@ void Update_FMAC_Coeffs(int stage, float b0, float b1, float b2, float a1, float
dyn_notch_filters[stage].b2 = b2;
dyn_notch_filters[stage].a1 = a1;
dyn_notch_filters[stage].a2 = a2;
// Если переходим из Bypass (b0≈1) в активный фильтр (b0<1),
// обнуляем состояние, чтобы избежать скачков
if (b0 < 0.9f) {
dyn_notch_filters[stage].d1 = 0;
dyn_notch_filters[stage].d2 = 0;
}
}
// Внутренняя функция для обработки одного каскада через FMAC
@@ -213,7 +219,7 @@ static int16_t FMAC_Step(fmac_coeffs_t *c, fmac_state_t *s, int16_t input) {
FMAC->WDATA = input;
uint32_t timeout = 1000;
while ((FMAC->SR & 0x01) && --timeout);
while (!(FMAC->SR & 0x01) && --timeout); // Ждем флаг VLD (Valid Data)
if (timeout == 0) return input;
main.c
+23 -23
View File
@@ -23,7 +23,7 @@ typedef struct {
} Telemetry_t;
#pragma pack(pop)
// 2. ПРОТОТИПЫ (Чтобы компилятор не ругался)
// 2. ПРОТОТИПЫ
void SystemClock_Config_160MHz(void);
void UART2_Init_921600(void);
void TIM6_Init_1000Hz(void);
@@ -54,31 +54,31 @@ int main(void) {
// В основном цикле while(1) внутри if (imu_flag)
while (1) {
if (imu_flag) {
imu_flag = 0;
IMU_ReadRawData();
DSP_AddSample((float32_t)raw_gx);
pkt.gx = raw_gx;
pkt.filt_gx = (int16_t)filt_gx;
// Заполняем частоты из dsp_manager.c
// extern float active_notch_freqs[3]; // Если компилятор не видит, добавьте в заголовок
pkt.freq1 = (uint16_t)active_notch_freqs[0];
pkt.freq2 = (uint16_t)active_notch_freqs[1];
pkt.freq3 = (uint16_t)active_notch_freqs[2];
while (1) {
if (imu_flag) {
imu_flag = 0;
IMU_ReadRawData();
DSP_AddSample((float32_t)raw_gx);
pkt.gx = raw_gx;
pkt.filt_gx = (int16_t)filt_gx;
// Заполняем частоты из dsp_manager.c
// extern float active_notch_freqs[3]; // Если компилятор не видит, добавьте в заголовок
pkt.freq1 = (uint16_t)active_notch_freqs[0];
pkt.freq2 = (uint16_t)active_notch_freqs[1];
pkt.freq3 = (uint16_t)active_notch_freqs[2];
UART_SendPacket(&pkt);
Set_Motor_Individual(m1_speed, m2_speed, m3_speed, m4_speed);
UART_SendPacket(&pkt);
Set_Motor_Individual(m1_speed, m2_speed, m3_speed, m4_speed);
}
if (dsp_buffer_ready) {
DSP_Process();
}
}
if (dsp_buffer_ready) {
DSP_Process();
}
}
}
// 4. РЕАЛИЗАЦИЯ ФУНКЦИЙ (Тут был провал - их не хватало!)
// 4. РЕАЛИЗАЦИЯ ФУНКЦИЙ
void SystemClock_Config_160MHz(void) {
RCC->CR |= RCC_CR_HSION;
settings/fft_az.dbgdt
+46 -31
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settings/fft_az.dnx
+1 -1
View File
@@ -25,7 +25,7 @@
<ShowSource>1</ShowSource>
</Trace1>
<DebugChecksum>
<Checksum>919959831</Checksum>
<Checksum>2949395940</Checksum>
</DebugChecksum>
<Disassembly>
<MixedMode>1</MixedMode>
settings/fft_az.wsdt
+9 -9
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